1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including content addressable memory cells (CAM cells) which compare data stored at their storage nodes with entered data. The present invention even more particularly relates to a semiconductor device including a highly integrated high-speed T-DCAM array made up of ternary dynamic CAM cells (T-DCAM cells) which store ternary data while refreshing it.
2. Description of the Related Art
The explosive growth of the Internet has increased the size of the tables required for network routers and switches, making it necessary to increase the table search speed. Conventionally, the calculation algorithm has been improved to speed up the table search. Such a method for enhancing the processing power, however, is approaching its limit. Furthermore, there is the problem of software solutions lacking in flexibility for supporting various network standards. Accordingly, the ternary content addressable memory (T-CAM) is attracting attention as a hardware solution for solving these problems.
A T-DCAM cell configuration of a ternary dynamic content addressable memory (T-DCAM) is described in Records of the 2000 IEEE International Workshop on Memory Technology, Design and Testing, pp. 101–105, 2000. FIG. 2 is a diagram of this cell configuration taken from FIG. 2 of the above document. This cell has storage nodes N1 and N2 made up of NMOS transistors T1, T2, T4, and T6 and capacitors C1 and C2 and stores ternary data.
The cell has an XNOR operation function implemented by the NMOS transistors T3, T4, T5, and T6 to compare its stored data with entered data.
First of all, its memory function will be described.
The ternary data uses three distinct values: data 1, data 0, and data X, which indicates the so-called DON'T CARE state. Assuming that a high voltage level represents a logic “1” and a low voltage level represents a logic “0”, the combination of the logic values of the storage nodes N1 and N2 corresponding to data 1 is “1” and “0” expressed as (1, 0); that corresponding to data 0 is “0” and “1”, or (0, 1); and that corresponding to data X is “0” and “0”, or (0, 0). The stored data is refreshed through the transistors T1 and T2, and read out and rewritten by use of sense amplifiers (not shown in the figure) connected to bit lines BL1 and BL2.
The XNOR operation function will be described below. The data to be compared with the stored data is ternary data and is entered through search lines SL1 and SL2. This ternary data uses three values: data 1, data 0, and data MASK, which indicates the so-called MASK state. In the comparison operation, if the entered data coincides with the stored data, since no current path is formed between a match line ML currently precharged at a high voltage and a discharge line DCL set at a low voltage (for example, ground potential VSS), the match line remains at the precharge voltage (the high voltage). If, on the other hand, they do not coincide, the match line is discharged since a current path is formed between the match line ML and the discharge line DCL.
A match line sense amplifier (not shown) senses changes in the voltage of the match line in the above operation to produce a comparison result. It should be noted that if the stored data is data X, or the entered data is data MASK, it is determined that the entered data coincides with the stored data since no current path is formed between the match line ML and the discharge line DCL.
Another T-DCAM cell configuration is described in Japanese Laid-Open Patent Publication 2002-197872. FIG. 3 is a diagram of this cell configuration taken from FIG. 2 of the above patent publication. This cell has an XNOR operation function implemented by the transistors T3, T4, T5, and T6, as does the cell described in Records of the 2000 IEEE International Workshop on Memory Technology, but the component configurations for their memory functions are different. Specifically, two NMOS transistors T9 and T10 are newly added to the configuration shown in FIG. 2. The cell shown in FIG. 3 having such a configuration stores ternary data, as does the cell shown in FIG. 2. The rewrite operation is carried out through the transistors T1 and T2, as in the cell having the configuration shown in FIG. 2. In the refresh operation, however, the present cell performs read operation in a different way, that is, by use of the newly added transistors T9 and T10. Specifically, when the transistors T9 and T10 are activated, signals corresponding to the conductive states of the transistors T4 and T6 determined by the stored data are generated on the bit lines BL1 and BL2.
Prior to the filing of this application, the present inventors studied how to increase the speed and the integration density of the T-CAM array and found that, of all prior art T-DCAM cells having a small cell area, the type of cell shown in FIG. 3 is important since it has the following two advantages.
One is that theoretically this cell can operate without capacitors, eliminating (or alleviating) the need for forming capacitors, which is an obstacle to miniaturization.
The other is that if this cell is formed of only NMOS transistors without using capacitors, the number of masks to be employed is reduced, which is expected to lead to reduced cost per bit.
The present inventors, however, have found that this cell has the following three problems.
The first problem is its reduced XNOR operation speed. As described above, the cell configuration shown in FIG. 3 is obtained by adding the transistors T9 and T10 to the configuration shown in FIG. 2. Such a configuration might increase the diffusion capacitances at intermediate nodes M1 and M1, delaying the output signal to the match line ML. Increased XNOR operation time is detrimental to speeding-up of the operation of the T-CAM array.
The second problem is the increased sense amplifier area. As described above, a T-DCAM array using the cell shown in FIG. 3 must sense (discriminate) not only the signal generated on the match line ML in the search operation but also the read signals generated on the bit lines BL1 and BL2 in the refresh operation. Therefore, sense amplifiers must be provided for all match lines and bit lines, reducing the cell occupancy ratio, which is detrimental to enhancement of the integration density of the T-CAM array.
The third problem is the deteriorated retention characteristic. Reducing the size of a transistor increases its leakage current, as is generally known. In the cell configuration shown in FIG. 3, an increase in the leakage currents of the transistors T1 and T2 leads to a reduction in the stored data retention time (or simply the retention time), requiring frequent refresh operation, which results in increased refresh power consumption of the T-CAM array.